Regviz

Silicon Labs /EFR32FG23B010F512IM48 /RAC_NS /IFPGACTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IFPGACTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/RAC_S/IFPGACTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)DCCALON 0 (DISABLE)DCRSTEN 0 (DISABLE)DCESTIEN 0 (DF3)DCCALDEC0 0DCCALDCGEAR

DCCALDEC0=DF3, DCESTIEN=DISABLE, DCCALON=DISABLE, DCRSTEN=DISABLE

Description

No Description

Fields

DCCALON

Enable/Disable DCCAL in DEMOD

0 (DISABLE): DC ESTI DISABLED

1 (ENABLE): DC ESTI ENABLED
DCRSTEN

DC Compensation Filter Reset Enable

0 (DISABLE): DC Comp out of Reset

1 (ENABLE): DC Comp in Reset
DCESTIEN

DCESTIEN Override for RAC

0 (DISABLE): DCESTI Disabled in MODEM

1 (ENABLE): DCESTI Enabled in MODEM
DCCALDEC0

DEC0 Value for DCCAL

0 (DF3): Decimation Factor 0 = 3. Cutoff 0.050 * fHFXO.

1 (DF4WIDE): Decimation Factor 0 = 4. Cutoff 0.069 * fHFXO.

2 (DF4NARROW): Decimation Factor 0 = 4. Cutoff 0.037 * fHFXO.

3 (DF8WIDE): Decimation Factor 0 = 8. Cutoff 0.012 * fHFXO.

4 (DF8NARROW): Decimation Factor 0 = 8. Cutoff 0.005 * fHFXO.
DCCALDCGEAR

DC COMP GEAR Value for DCCAL

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data